资源列表
debussy53
- Ultimate CRC is a CRC generator/checker. Using generics the core can be fully customized. It creates a function of the data input and the CRC register using XOR-logic. Although the levels of logic gets very high for wide data inputs, the throughput s
gen_clk
- 通过FPGA产生时钟信号，通过FPGA产生时钟信号-通过FPGA产生时钟信号
DDR_Xilinx
- xilinx公司DDR控制ipxilinx公司DDR控制ip-xilinx公司DDR控制ip
1553B
- 1553协议控制， 1553协议控制-1553协议控制
vad_DTW_real_Time
- voice activity detection and dynamique time warping in real time DSP simulink
TamilTTS
- LNCS 3285 - Introducing Pitch Modification in Residual Excited LPC Based Tamil Text-to-Speech Synthesis
FFT
- 8 point FFT written in Verilog
floating_point_addition_subtraction
- Simple floating point addition unit written in Verilog
5_band_graphic_equalizer
- 5_band graphic equalizer circuit using a single IC-chip
PC_Control_temperature
- PC与单片机双向通讯智能温控程序,PC与单片机通信控制温度-PC commnicate with singlechip(AT89S52),and control the temperature
hdbn
- vhdl语言实现hdb3编码，也可就行hdb2编码，综合后实现hdb3编码的硬件实现-vhdl language hdb3 coding, also may line hdb2 code, after the realization of integrated hardware encoding hdb3
fir
- 用verilog编写的fir滤波器程序,可实现fir的硬件综合-Fir filters using verilog written procedures