资源列表
xunzhi
- DSP C5400的数据寻址汇编程序，含各种数据寻址方式，包括立即寻址，绝对寻址，累加器寻址，直接寻址，间接寻址，存储器映像寄存器寻址和堆栈寻址-DSP C5400 data addressing assembler, containing a variety of data addressing modes, including an immediate addressing, absolute addressing, accumulator addressing, direct addres
IIR
- 无限冲击响应(IIR)滤波器设计，用于DSP芯片开发-Infinite impulse response (IIR) filter design for the DSP chip development
at89c52_cn
- AT89C52 单片机c52系统的详细资料-AT89C52 DateSheet
FIR
- 有限冲击响应滤波器(FIR)的滤波器设计，用于DSP芯片开发-Finite impulse response filter (FIR) filter designed for the DSP chip development
rotate_switch
- 双触点旋转开关verilog驱动，内置消抖模块。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-Double-contact rotary switch verilog drive, built-in modules eliminate shaking. Prepared source files using the emacs, iverilog simulation adopted, within the simulation images png screen
jitter_eliminate
- verilog描述的实用消抖电路，采用三个D触发器和一个JK触发器。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-verilog descr iption of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted
trigger
- D触发器和JK触发器，使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-D flip-flop and JK flip-flop, use emacs to prepare source file, iverilog simulation adopted, within the simulation images png screenshots
freq_divider
- 8bit分频器，最高256*2=512 分频，使用emacs编写源文件，iverilog仿真通过-8bit divider, the maximum 256* 2 = 512 min frequency, use emacs to prepare source file, iverilog simulation success
keshe
- 基于ａｔ８９ｓ５２设计的等精度频率计源程序-Based on the design at89s52 source such as precision frequency counter
TraditionalToSimplified_fat
- 中文繁简词汇的转换，可实现繁体-简体 和 简体-繁体的转换-Chinese simplified vocabulary conversion can be realized Traditional- Traditional and Simplified- Traditional conversion
cfft
- 用verilog语言编写的基4FFT，采用CORDIC算法实现的，仿真过，结果很好！-I use verilog language to design a FFT base 4,and use CORDIC arithmetic to achieve this. last , I test it, it looks very good