资源列表
dpram_fpga
- 这是我用vhdl语言，在fpga内部做了一个双口ram的程序。我的邮箱：wleechina@163.com-This is the language I used vhdl in fpga done an internal dual-port ram procedures. My mail : wleechina@163.com
9315
- EP9307程序 非常珍贵 ------EP9307程序 非常珍贵-EP9307 procedures precious ------ EP9307 precious procedures
UCOSAVR128V28
- 将本站的UCOSFORAVR128V276版本升级到了280版，修正原来的中断定义错误，并仿真调试已通过。-UCOSFORAVR128V276 the site will upgrade to version version of the 280, that the interruption of the original definition errors, and debugging simulation has passed.
EVAL_C5131
- C89c51 usb驱动程序,实现了usb转串口的功能,提供了一个虚拟的串口-C89c51 usb driver, realizing the usb serial transfer function provides a virtual serial port
TimerMode-PWM-lpc900
- PHILIPS LPC900 PWM CRTL 时间可调 -PHILIPS LPC900 time adjustable PWM CRTL
div5_verilog
- 5分代码及说明，verilog代码，几乎所有的IC面试都会问到这个问题，所以总结了一下发了上来，共同学习！-5 pm code and explanations verilog code Almost all the interviews will IC asked this question, summed up in the ranks about fat, learn together!
tcm_decode
- TCM解码，VHDL代码，是我在工作中做的工程代码，时序稳定，里面有syn以及软判决的算法，经典-TCM decoder, VHDL code, yes, I do work in the project code, timing stability, There are syn and soft-decision algorithm, classic!
m1601
- 关于显示的程序，采用太阳人公司生产的液晶模块，可直接引用。-show on the procedures for using solar company production of LCD module, which can be directly invoked.
1024_FFT
- 1024点FFT快速傅立叶变换，包含说明文档和VHDL源代码，16位输入/输出，带DMA功能，xilinx的ip-1024-point FFT fast Fourier transform, and includes documentation, VHDL source code, 16 input / output, with DMA function, the ip xilinx
CRC_VHDL
- 可配置CRC参考设计 xilinx的ip，参考设计文档CRC_xapp562[1].pdf，VHDL语言编写的代码，包含仿真所需文件-configurable CRC Reference Design xilinx the ip, CRC_xapp562 reference design document [1]. pdf, prepared by the VHDL code The simulation includes the necessary documents
man_Verilog
- 曼彻斯特编解码，是Verilog语言代码，不多介绍了，用途非常广泛了-Manchester encoding and decoding is the Verilog language code, introduced a few, a very extensive use
trellis_verlog
- ATSC发送端部分，ATSC标准特有的TCM编码，共6个文件，包含tb文件，已通过仿真，没有问题，verilog代码-ATSC transmitter, the ATSC standard TCM unique coding, a total of six documents, tb-contained documents, had passed through simulation, no problem, verilog code