资源列表
Bucket-shift-register
- 桶型移位寄存器。主要实现循环移位功能。模块单一化，有助于移植，并方便使用人员快速理解并应用-Bucket shift register.The main realization of cyclic shift function.Single module, help to transplant, and easy to use personnel to quickly understand and apply
wannianli(51)
- 这是一个基于51单片机的万年历代码。包含串口通信、PWM、中断、ADC、按键菜单以及时钟芯片和温度传感器的使用-This is a calendar based on 51 microcontroller code. Include serial communication, PWM, interrupt using ADC, buttons and menus as well as the clock chip temperature sensor
TLV2553
- 本代码是MSP430项目工程，实现了一个高精度数据转换器。 -This source code is a example of MSP430 Project for your Precision Data Converter.
ADXL335
- ADXL335加速度计性能概述，工作原理简介-ADXL335 accelerometer performance overview, introduction of working principle
VHDL-clock
- 用VHDL写的数字钟程序，能够实现显示时分秒，时间可以调节，还能设定闹钟-Written in VHDL,the digital clock procedures can display every minute, the time can be adjusted, but also to set the alarm
STM8toHT16211
- STM8实现驱动HT1621点亮段式LCD屏幕的程序-STM8 achieve segment LCD driver HT1621 lit screen procedure.
Arduino-sample-code
- LCD diplay for HX7-LCD diplay for HX711
modulation-and-demodulation
- 调制与解调系统的FPGA设计实现,包括2-ASK调制和解调,2-FSK调制和解调,2-PSK调制和解调,QPSK调制和解调,PPM调制和解调的verilog源代码。-FPGA design implementation of modulation and demodulation system, including 2-ASK modulation and demodulation, 2-FSK modulation and demodulation, 2-PSK modulation and
MultHalfBand
- 多级半带滤波器的FPGA实现,采用6级滤波器实现的采样频率由3200Hz降为50Hz的抽取系统，前5级为半带滤波器,最后一级为普通FIR滤波器-Multi-level half-band filter FPGA, using six filters for sampling frequencies 50Hz down to 3200Hz extraction system for the front five and a half-band filter, the last stage of
MultCIC
- 三级梳状积分CIC滤波器的FPGA实现代码，包括积分模块，抽取模块和梳状模块以及顶层模块的实现代码-Three integral CIC comb filter FPGA implementation code, including the integration module, extraction module and a comb and a top-level module module implementation code
wcdma.v
- 无线通信FPGA设计例13-6源代码，WCDMA系统小区搜索的FPGA实现 -Example 13-6 FPGA design of wireless communication source code, FPGA implementation of WCDMA system cell search
RLS.v
- 用verilog实现的一个2抽头RLS自适应滤波器的代码-A realization with verilog HDL code of a two-tap RLS adaprive fliter