资源列表
cdk.tar
- 从cdk官网下载的最新cdk库完整可编译源码-the latest complete lib source code from cdk official site
motion_driver-5.1.2
- MUP6050官方dmp库5.1.2，直接输出四元数，避免复杂滤波-6-axis platform independent solution based on Embedded MotionApps 5.1 architecture. Bug fixes and new APIs added.
AM23XX-(1)
- AM2301的51驱动文件，亲测可以使用，希望大家多多交流共同提高-AM2301 51 driver files, you can use the pro-test, we hope to improve the exchange of common
fap
- Program for Connect Nav Plus
stm3210e-eval_sch
- stm32开发板的sch原理图，适合于初学者自己画板子，可以较为简洁-sch stm32 development board schematics, suitable for beginners own child drawing board, can be more concise
speak3
- 在FPGA上实现简易电子琴功能，再加上了一个实时时钟功能，时钟很稳定，很精准。-The realization of simple electronic organ function in the FPGA, coupled with a real time clock, the clock is very stable, very accurate.
singt
- 使用FPGA产生一个正弦波，里面带有嵌入式逻辑分析仪的仿真文件。-Using FPGA to generate a sinusoidal wave, simulation files with embedded logic analyzer.
PLL
- fpga锁相环的使用例程，可以教您如何使用PLL锁相环。-FPGA phase-locked loop using the routines, can teach you how to use PLL phase locked loop.
music
- VHDL电子琴，采用vhdl编写，通过蜂鸣器发出7种不同频率的音阶实现简易电子琴功能。-VHDL electronic organ, written by VHDL, the realization of simple electronic organ function in 7 different frequency scale through the buzzer.
cnt60
- 60秒加一计数器，实现0到59秒计时。可以参照此例编写一个FPGA时钟，代码用VHDL编写。开发环境为quertues ii9.1.-60 seconds with a counter, to achieve 0 to 59 seconds. Can refer to this case to write a FPGA clock, the code written in VHDL. Development environment for quertues ii9.1.
cnt24
- VHDL24秒篮球倒计时,VHDL编写，实现23到0计数。quartues ii 9.1编写的。-VHDL24 sec basketball countdown, written in VHDL, to achieve 23 to 0 count. Quartues written in II 9.1.
ZigBee-Fuction
- 自己总结的ZigBee函数功能说明，希望对初学者有所帮助，可以看下，自己的原创-The ZigBee function summing up their own show, I hope to help beginners, can see, their own original