资源列表
memory
- The pipeline SPIN VHDL code (memory part)
fetch
- The pipeline SPIN VHDL code (fetch part)
TimeClock
- 能够在max3上显示24小时，并且具有定时功能，能够设定闹钟，具有正点报时-Max3 can display 24 hours, and has a timer function, be able to set the alarm, with punctual timekeeping
execute
- The pipeline SPIN VHDL code (execute part)
decode
- The pipeline SPIN VHDL code (decode part)
wendu
- DS18B20的基于430的程序，经过测试。完全能用-430 Based on the DS18B20 procedures, tested. Used completely
control
- The Pipeline SPIN model using VHDL
clock
- 基于51单片机的万年历程序。经过测试，完全能用-51 MCU-based calendar program. After testing, can be used completely
main
- 主程序等待外部中断触发的噪声报警，LED显示运行状态-Main program wait for an external interrupt trigger noise alarm, LED display operating status
waveform
- The waveform of pulse generator code
pulse_gen
- Pulse generator using VHDL for most of FPGAs
Murphytalk.tar
- Murphytalk qt 下 输入法，可支持嵌入式。-Murphytalk qt under the law, can support embedded.