资源列表
Exercise6
- Full version for "Exercise #6" for SSD4.
Exercise5
- Full version for "Exercise #5" for SSD5 course.
OV7620
- 0v7620摄像头二值化串口调试，需串口调试助手，方便调试-0v7620 camera binarization serial debugging, need serial debugging assistant, to facilitate debugging
bluetooth
- xs128串口调试，，打开串口调试软件，发送和接受测试-xs128 serial debugging, open the serial debugging software, send and receive test
qudong
- B车bts7960驱动模块测试，注意，驱动芯片已用电源5V使能，因此只需要控制pwm即可-B car bts7960 driver module testing, Note that the driver chip has 5V power supply is enabled, so you can only control pwm
nelson
- 实现了在xs128maa上的MPU6050数据初始化和基本的数据返回-Achieved in the xs128maa on MPU6050 data initialization and basic data back
LPC2368datasheet-chinese
- lpc2368的中文资料 中文的数据手册-lpc2368 of Chinese Information Chinese data sheet
Digital-lock-design
- 1、了解数码锁的工作原理。 2、了解数码锁的实现方法。 3、进一步掌握4×4键盘的扫描的实现过程 -1, to understand the working principle of the digital lock. 2, to understand the implementation of digital locks. 3, to further understand the 44 keypad scanning the implementation process
Taxi-meter
- 1、了解出租车计费器的工作原理。 2、学会用VHDL语言编写正确的七段码管显示程序。 3、数量掌握用VHDL编写复杂功能模块。 4、进一步数量状态积在系统设计中的应用。 -1, to understand taxi meter works. 2, learn the proper use of VHDL language program seven-segment LED display. 3, the number of master with VHDL complex fu
Digital-stopwatch
- 1、了解数字秒表的工作原理。 2、进一步熟悉用VHDL语言编写驱动七段码管显示的代码。 3、掌握VHDL编写中的一些小技巧。 -1, to understand the working principle of digital stopwatch. 2, more familiar with the use of VHDL language driver seven segment display code. 3, master VHDL prepared some of the t
Multi-function-digital-clock
- 1、 了解数字钟的工作原理。 2、 进一步熟悉用VHDL语言编写驱动七段码管显示的代码。 3、 掌握VHDL编写中的一些小技巧。 -1, to understand digital clock works. 2, more familiar with the use of VHDL language driver seven segment display code. 3, master VHDL prepared some of the tips.
Digital-frequency-meter
- 1. 了解等精度测频的方法和原理。 2. 掌握如何在FPGA内部设计多种功能模块。 3. 掌握VHDL在测量模块设计方面的技巧。 -1 understand other precision frequency measurement methods and principles. (2) learn how to design a variety of functions within the FPGA module. 3 master VHDL module design aspec