资源列表
stm32
- 基于arm m3示波器，信号发生器系统控制及lcd控制等源代码-Source code based on ARM m3 oscilloscope, signal generator system control and lcd control
ledvhd
- ISE与VHDL入门程序，使用DCM分频实现LED的控制。-ISE and VHDL entry procedures with DCM divide LED control.
UART0407
- ise平台模拟UART，并与PC机实现收发（+1）-ISE platform simulation UART and transceiver.
fpga
- 嵌入式fpga示波器采集配置及源码 采用keil4，兴建工程-The embedded FPGA oscilloscope acquisition configuration and source
dds
- 基于FPGA，利用vhdl语言结合matlab工具实现dds,已经仿真-Based on FPGA, VHDL language with matlab tools to achieve DDS, has simulation
printf
- 本函数实现了打印的功能，主要针对于哪些没有字库的屏提供了很好的显示界面操作-This function implements the print function, mainly focuses on what doesn t the character screen provides a good display interface
leddownloaduart
- DSPF28XX系列通过串口下载的LED例程，实验成功。-Series DSPF28XX downloaded through the serial LED routines, the experiment was a success.
clk_div
- 实现时钟的四分频和16分频，用Verilog语言编写，并经过Quartus仿真-Clock divided by four and divided by 16
CNTRTEST3_7tx_rx_0422
- 在ISE12.4与TMS320F2812的XINTF接口，实现数据收发-In ISE12.4 TMS320F2812 the XINTF, data transceiver
chuankou
- 基于FPGA，利用vhdl语言实现串口通信，程序已仿真-Based on FPGA, VHDL language serial communication, a simulation program
vhdl-_hamming
- 基于FPGA，利用vhdl语言实现hamming编码的一段程序，已经仿真过-Based on FPGA, VHDL language hamming coding a program simulation
digital-clock
- 采用verilog语言将输出频率分频实现数字钟的基本功能：如时间显示，定点报时，整点报时，倒计时等。-Using verilog language to realize the basic function of digital clock by cut the output frequency , such as showing time, designated time,, countdown, etc.