资源列表
interrupt
- Freescale K60 中断配置 优先级 中断入口-Freescale K60 interrupt configuration priority interrupt entry
core
- Freescale K60 内核启动文件 程序代码-The Freescale K60 kernel boot file code
vectors
- Freescale K60 中断向量 vectors 程序代码-The Freescale K60 Interrupt vector vectors code
wdog
- Freescale K60 watchdog 程序代码，软件watchdog-The Freescale K60 watchdog program code, software watchdog
pll
- Freescale K60 PLL时钟配置 各种PLL模式之间转换-The the Freescale K60 PLL clock configuration between the various PLL mode conversion
state-machine
- Verilog HDL编写的简单状态机程序。-The Verilog HDL written a simple state machine program.
serial
- Verilog HDL编写的串口通信程序。-The Verilog HDL written serial communication program.
seg71
- Verilog HDL编写的7段数码管显示程序。-7-segment LED display program written in Verilog HDL.
BCD
- Verilog hdl编写的二进制转BCD码程序-BCD binary switch program written in Verilog hdl
The-hardware-principle-diagram
- fpga嵌入式项目开发三位一体实战精讲的硬件原理图-hardware schematic fpga embedded project development trinity combat Jingjiang
sourcecode
- 《FPGA嵌入式项目开发三位一体实战精讲》一书的程序代码-The FPGA embedded project development trinity combat succinctly book code
ram-and-fifo
- ALTERA公司的一些关于RAM，FIFO等IP核的技术文档，对用到IP核存储设备的读者很有用！-ALTERA Company RAM, FIFO IP core technical documentation, readers used IP core storage devices useful!