资源列表
cr_counter
- 视频图像的行列计数器基于VHDL的实现，已经调试仿真通过-Video images VHDL-based implementation of the ranks of the counter has been adopted debugging emulator
wishbone_i2c_master
- 本帖最后由 NovaCao 于 1-18-2009 18:02 编辑 使用Quartus II进行仿真 QQ：44425312 QQ群：50585234（群名称：FPGA4u） gtalk：fpgaforu@gmail.com 网站：www.fpga4u.com 淘宝网店：http://shop34914329.taobao.com/ 我们以一个计
iic.cx
- 本帖最后由 NovaCao 于 1-18-2009 18:02 编辑 使用Quartus II进行仿真 QQ：44425312 QQ群：50585234（群名称：FPGA4u） gtalk：fpgaforu@gmail.com 网站：www.fpga4u.com 淘宝网店：http://shop34914329.taobao.com/ 我们以一个计
FPGA2SRAM
- verilog code that can implemented on ACEX1k FPGA for a SRAM-verilog code that can implemented on ACEX1k FPGA for a SRAM
Sevenseg
- verilog code for a decoder that converts bcd to seven segment leds
freq
- a verilog hdl code that contains scr ipt for dividing frequencies in ACEX1K Altera FPGA Board.
shiftrot
- A verilog hdl code for rotational shift register
spioreg
- a verilog code for spio register
DE1_pin_assignments_TFT_NEC6446
- de1 assignments for nec6446 tft vga display
2
- VHDL code for bcd7 registry
FIR
- The FIR digital filter algorithm is simulated and synthesized using VHDL
FFT
- Fast Fourier Transform in vhdl and matlab