资源列表
dctalgo
- vhdl coding for dct algorithm
addersubtractor10
- vhdl coding for adder subtractor used in dct
signaddsub12
- vhdl coding for signed adder substractor
vhl_application
- VHDL source code for a controller application
ddr_sdr_latest.tar
- 一款DDR400的驱动程序，使用VERILOG语言，在LATTICE—ECP2m的FPGA芯片中实际测试。-A DDR400 driver, using VERILOG language, LATTICE-ECP2m actual test of the FPGA chip.
vga_lcd_latest.tar
- 此VGA/LCD控制器是revB.3版本的基于WISHBONE总线，适用于驱动CRT和LCD显示屏的嵌入式VGA驱动。-VGA/LCD Controller core is a WISHBONE revB.3 compliant embedded VGA core capable of driving CRT and LCD displays. It supports user programmable resolutions and video timings, which are limit
usb_latest.tar
- 用VHDL语言编写的USB 2.0IP核。USB 2.0的传输速率是高速率480 Mb/s，需要再外扩一个PHY。-This is a USB 2.0 compliant core，USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core.
ldpc_decoder_802_3an_latest.tar
- 适用于10GBase-T的以太网(802.3an协议)LDPC解码器, 用VHDL语言编写，可以应用在LATTICEXP2系列芯片上，基于Gallager算法。-LDPC decoder for 10GBase-T Ethernet (802.3an), based on Gallager s A algorithm
ldpc_encoder_802_3an_latest.tar
- 适用于10GBase-T的以太网(802.3an协议)LDPC, VERILOG语言编写，可以应用在LATTICEXP2系列芯片上，基于Gallager算法。-LDPC encoder for 10GBase-T Ethernet (802.3an), based on Gallager s A algorithm
Datasheets
- 关于ALTERA DE2板上的文档资料，包括应用实例，用户文档和板上常用器件的技术文档-datasheets of ALTERA DE2
FPGA
- 使用VHDL实现的串口通信程序，主要完成利用串口收发数据等功能 -Using the VHDL implementation of the serial communication program, primarily the completion of functions such as send and receive data using serial port
FPGA_USB
- 使用VHDL实现利用USB端口通信的程序，主要完成在FPGA上的通信功能-The use of VHDL implementation procedures for the use of USB port communications, primarily on the completion of the communication function in the FPGA