资源列表
ADD_SUB_32bit
- 加减法器，可实现有无符号数的加减法-Modified instruments used, can be realized whether the number of addition and subtraction symbols
uart16550
- Implementation of the UART 16550 model with verilog langugue
caideng_dandian
- 彩灯控制电路，单点移动模式，一个点在8个发光二极管上来回的亮。-Lights control circuit, single-point move mode, a point in eight bright LEDs on the back and forth.
ALU
- David pattern 的ALU模型编码-David pattern in the ALU model code
Floating-Point-Adder
- 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
VHDLsample
- 英国诺森比亚大学的vhdl语言例程集锦，英文原版。 包含很多优秀的VHDL语言范例，可供学习。所有程序均可在符合IEEE标准的模拟器上模拟。-This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The exampl
SeniorFPGADesign
- 清华大学电子工程系的FPGA高级设计技巧教程-Department of Electronic Engineering of Tsinghua University, Senior FPGA Design Basics
drive
- TCD1300ccd的驱动，是用 Verilog实现的
automat
- automat stane - vhdl
Rejestr_przesuwny
- shift-register, model-vhdl
dekoder
- decoder in vhdl - model struct
bookVHDL
- book_vhdl - english_language