资源列表
44_reg_counter
- 用VHDL写的计数器程序例子，
DigitalWatch
- Digital watch write in Verilog HDL language simulate the real clock in Atera DE2 development board
rs232
- uart rs232 receiver and transmiter
qiangdaqi
- 六路数字式抢答器的主要仿真程序，容纳6组参赛的数字式抢答器，当第一个人按下抢答按钮时，其他组的按钮不起作用。当主持人按下“复位”按钮，所有组的按键才可用。-Six Road, a major digital answering device simulation program, up to 6 groups participating in the digital answering device, when the first one to answer in the button pres
FPGA
- FPGA入门系列实验教程 FPGA入门系列实验教程-Introduction to FPGA tutorial series of experiments
LEDsevensegmentdecode
- LED seven-segment decoding very good use of ~
CPU-to-VHDL
- CPU realization using VHDL CPU realization using VHDL-CPU realization using VHDLCPU realization using VHDLCPU realization using VHDL
TB_VHDL(adder)
- 加法器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about adder for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example
counter
- 计数器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about counter for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example
Text-IO
- 基于VHDL的Testbench读取文件的编写，很有用的 基于VHDL的Testbench读取文件的编写，很有用的-VHDL Code text_io for the "Simple Test Bench" example VHDL Code about text_io for the "Simple Test Bench" example
multiplier
- 个人收集的各种乘法器vhdl源代码，都经过验证，可以直接使用的。-Collected a lot of multiplier vhdl source code
inputoutput_textio
- 关于VHDL读取文件的testbench编写的ppt介绍，挺有用的-testbench for text_io,it is very useful,isn t it.testbench for text_io,it is very useful,isn t it.