资源列表
jiaotongdeng
- 一个用VHDL编写的在CPLD上实现模拟交通灯的程序源代码-a VHDL prepared by the CPLD on the analog signal source code
watch2
- vhdl实现watchdog，在逻辑中可以加入本模块，实现看门狗。-VHDL achieve watchdog, the logic of the modules can be added to achieve watchdog.
20060412183015974
- 是关于dct的Verilog HDL源代码和测试程序-on the Verilog HDL source code and testing procedures
traffic_light
- 一个用verilog编写的模拟交通灯控制的源代码。模拟在十字路口的双向交通灯。-a prepared using Verilog simulation of traffic lights to control the source code. Simulation at the crossroads of two-way traffic lights.
sdramusevhdl
- sdram的vhdl实现 本文介绍了sdram的控制时序特征，并介绍了采用vhdl语言实现的sdram控制器的关键技术-SDRAM This paper introduces the realization of SDRAM timing control features, and introduces the VHDL language SDRAM controller of the key technologies
fft_debug
- 能进行32位浮点数fft运算的VHDL描述。-can float for 32 fft Operational VHDL descr iption.
scu_all_fpga
- 大型嵌入式设备FPGA程序，verilog HDL语言，实现DLL和PCM码流分流。-large embedded FPGA procedures, Verilog HDL, DLL and achieve PCM stream diversion.
addch1
- 用vhdl语言设计CPU中的一部分：加法器的设计，包括多种加法器的设计方法！内容为英文-design using VHDL language part of the CPU : Adder design, Adder including multiple design! As for the English
mul6
- 用vhdl语言设计CPU中的一部分：乘法器的设计，包括多种乘法器的设计方法！内容为英文-design using VHDL language part of the CPU : multiplier design, Multiplier including multiple design! As for the English
DesignCompiler
- Design Compiler使用简要说明,说明了用这一工具进行综合的过程 -use Design Compiler brief statement, the use of this tool for integrated process
clockv
- 使用Verilog语言编写的数字钟程序.有慢校时,快校时,闹钟等功能.-use Verilog language prepared by the digital clock procedures. Schools are slow, quick school, alarm clock functions.
1.i2c_slave
- I2C的slave端程序,用于响应master端,并进行通信-the slave I2C software, in response to the master terminal, and communications