资源列表
shi
- 数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on
uart_ise_vhdl
- fpga里实现 uart 经典 vhdl语言写的 ise工程文件-fpga implementation in vhdl language classic uart of ise project file
CPCI_1.0
- 多功能卡的源代码，verilog编写，用于多功能的数据接收-verilog code of mutiple function card
LCD_Driver
- this a LCD Driver VHDL code -this is a LCD Driver VHDL code
verilogchap12
- 王金明verilog书中的大量实例 适合初学者使用-Wang Jinming verilog book suitable for beginners to use a large number of examples
10chapter
- 王金明verilog书中第十章的例子 适合初学者-Wang Jinming verilog example Chapter book for beginners
9
- 王金明verilog书中第9章的例子 适合初学者-Wang Jinming verilog book examples of Chapter 9 for beginners
8
- 王金明verilog书中第8章的例子 适合初学者-Wang Jinming verilog book example of Chapter 8 for beginners
7
- 王金明verilog第7章 适合初学者-Wang Jinming verilog Chapter 7 for beginners
XHDL3Version3·2·37
- vhdl语言和verilog语言转换工具 能很容易的实现两种语言的相互转换-verilog language vhdl language and conversion tools can easily achieve the conversion between two languages
dds
- dds算法的fpga实现 altera 根据不同设置，输出不同频率的信号源-dds algorithm to achieve fpga set according to different altera, the output of the signal source at different frequencies
cordiccos
- cordic算法的fpga的实现 采用altera芯片-cordic realization algorithm using fpga chip altera