资源列表
fifo8
- FIFO 源程序，verilog HDL实现，自己验证过，没问题-FIFO source, verilog HDL to achieve their own verified, no problem
edge_check2
- 一种实用的上升沿检测程序，可用于上升沿检测，或根据上升沿生成高低电平等-Rising edge of a practical testing procedure can be used for rising edge detection, or generated in accordance with the high-low, such as rising edge
8255A2.9
- 采用Verilog语言实现了8255A的功能，并下载到了FPGA上进行了验证-this project achieved the goal of realizing the function of 8255A which is widely used in many digital designs.
EPM1270_trafficlight
- VHDL 学习很好的一个例程，包含思路方法，以及源码解释-A good example for VHDL study.
fulladder
- 这是一个基于嵌入式的利用硬件高级描述语言编写的全加器程序，可以满足二进制全加的功能。-This is a use of embedded hardware-based high-level language to describe the All-Canadian program to meet the functions of the binary full adder.
POC
- 东南大学学生数字系统设计实验：用VHDL语言编写Printer与CPU互连的接口程序-Southeast University students in the experimental digital system design: VHDL language with Printer and CPU interface interconnection procedures
138
- 用vhdl 语言实现138译码器，用vhdl 语言实现138译码器，-vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl
lab2-2
- 4位二进制加法器，vhdl实现,外带译码器部分，清晰简洁，可读性好-4-bit binary adder, vhdl achieved decoder part of the bargain, clear and concise, readable good
48_4.12
- 网络通信中的MII接口 通常将4位nibble数据送出，此程序将4位数据组合成8位数据并行输出（8比特==1个字节）。。完全可用 同时包含84转换-The MII network interface usually sent four nibble data, this procedure will be 4-bit data into 8-bit parallel output data (8 bits == 1 byte). . Completely available at the
EPM1270_adder
- vhdl 学习基础实例,有利于VHDL入门很有帮助-A good example for VHDL study.
EPM1270_comparator
- vhdl 基础例程，比较器，有利于VHDL入门学习-A good example for VHDL study
EPM1270_multiplier
- VHDL 乘法器 源代码，很好的VHDL 入门学习例程序-Multiplier VHDL source code, a good learning example VHDL entry procedures