资源列表
dekoder
- dekoder code s Gray to cod „ 1 from 16”. This is program i VHDL-dekoder code s Gray to cod „ 1 from 16”. This is program i VHDL
Counter_VhdlCode
- it is a simple counter written in vhdl , can be simulated using model sim worked on xillinx for fpga.
Frequency_Divider_VhdlCode
- a very good frequency divider code for fpgas>
A_study_about_FPGA_based_digital_filters
- Digital hilbert transformers for FPGA-based phase-locked loops
avalon_pwm
- altera公司的PWM设计，非常详细！-altera' s PWM design, very detailed!
1(1)
- Debussy和MODELISM混合的使用 Debussy和MODELISM混合的使用-Debussy and MODELISM Debussy and MODELISM
PPort
- 计算机并行接口与单片机接口的CPLD烧写文件，是ALTERA芯片的-Computer parallel port interface of the CPLD and MCU programmer document ALTERA chips
1(2)
- 署名FPGAexpress_intr介绍的一本好书-FPGAexpress_intr
1(3)
- 确实是 介绍synplicity.的一本好书-synplicity.synplicity.
Crash.the.Simulation.Barrier
- 确实是 介绍synplicity.的一本好书-synplicity.synplicity.
Chapter11
- markov algorithm how to use this algorithm with fint state machine
VERILOGchaffic
- 用VERILOG 语言编写的十字路*通灯程序-TRAFFIC LIGHT