资源列表
KIT1234
- This used how to connect the DE2 kit for the external devices-This is used how to connect the DE2 kit for the external devices
lcd_B
- lcd module interfacing inintialization example
clock
- 用verilog实现的数字钟，已经在ACTEL公司的A3P030的开发板上成功运行-Digital clock with Verilog , successfully ran on the board of ACTEL A3P030
bcd-decoder
- 用Verilog实现的BCD译码器. 经Quartus||波形仿真无误 经硬件验证无误-BCD decoder Realized by Verilog
EP3C8020111219125810_ROM_OK5
- 采用DSP builder v9.1实现正交两路单频输出，已经在EP3C80上面跑通，经实际验证是正确的。此例程非常简洁明了，可以作为DSP builder的入门示例。里面已经包含了生成好的modelsim仿真示例和仿真结果。-Achieved using DSP builder v9.1 orthogonal two single-frequency output, has been run through the EP3C80 above, are proven to be correct.
VerilogHDLdesignexample
- VerilogHDL设计实例及其仿真与综合-VerilogHDL design example and its simulation and synthesis
VerilogHDLAD7862
- 运用VerilogHDL实现AD7862的数据采集设计-VerilogHDL achievement of the use of the data collection design AD7862
143637___fpgas_and_cplds
- vhdl couter 3 bit and make by vhdl and vhdl
jtag_uart
- Configuration and usage of Altera s JTAG UART.
VAEP2C8
- FIRST DRAFT USER MANUAL ABOUT VA-EP2C8 FPGA DEVELOP BOARD
cycloneIII3c120dev
- This document describes the hardware features of the Cyclone® III development board, including detailed pin-out information to enable you to create custom FPGA designs that interface with all components of the board.-This document describes the ha