资源列表
checksum_master_onchip2.7z
- 学习sopc builder当中自定制元件的最经典最全面的例子，绝对超值-Learning sopc builder customized component among the most classic examples of the most comprehensive, the absolute value
ourdev_185208
- 本讲义主要是讲的Verilog语言，是东南大学讲义，可以对这门语言有个初步的了解。-The lectures are mainly talking about Verilog language, the Southeast University, notes that this language has a basic understanding of.
key
- cyclone系列下，采用计数器现实案件消抖的verilog HDL语言源码-series under the cyclone, the consumer cases Buffeting counter the reality of the verilog HDL language source code! !
sdram_verilog
- sdram的使用，使用verilog HDL来实现对sdram的操作！对时序和语言功底有要求！-sdram use verilog HDL used to achieve operation of the sdram! On the timing and language skills required!
state
- verilog HDL下有限状态机（FSM），麻雀虽小，但五脏俱全！值得一看-under the verilog HDL Finite State Machine (FSM), the sparrow may be small, but is a fully-equipped! Worth a visit! !
instmemory
- Instruction memory in VHDL
Example-2-1
- 编译过正确的fpga开发实例，很是适合也新手入门。fpga开发新手间的交流-fpga
Example-3-1
- 经过验证的经典实例，完全正确的。适合于入门新手的实例，仅供交流使用。-fpga exampe
CAST_sdr_sdram_ctrl-xact
- Single Data Rate Mobile SDRAM Controller Core with AHB Interface
des_Vhdl
- VHDL & Verilog Synthesizable model of the Data Encryption Standard (DES)
1137198913
- altium designer 6 Training for FPGA,Software andSystemsDevelopmentEmbedded Intelligence Training
UART_FPGA_design
- FPGA通用异步收发器设计，代码均在WORD文档里，含详细说明，不错的。-UART FPGA design, the code in the WORD document, the content in detail, good.