资源列表
fir2
- 用memory编写的FIR，比较适合入门学习，已经过仿真，-Prepared with the memory of FIR, more suitable for entry-learning, has been simulation,
hdlc_1
- 高级链路控制的HDLC发送，写的还行，需要使用93版本的VHDL格式-Advanced Link Control HDLC to send, write that still need to use the 93 version of the VHDL format
fir_memory
- 用memory编写的verilog代码，可用于工程应用，已经过仿真-Verilog code written with the memory can be used for engineering applications, has been simulation
LAOWAI
- 一个老外写的HDLC协议，包括说明文件，很有参考价值-Written by a foreigner HDLC protocols, including documentation, of great reference value
cf_fft
- 傅里叶变换器，用于数字信号处理的verilog代码-Fourier converters for digital signal processing verilog code
ALU_ZMR
- 简单的ALU运算模块，可实现加法减法移位等运算-A simple ALU operation modules, enabling operations such as addition subtraction shift
qiangdaqi1
- 这是一个数电的4选手抢答器的设计报告 内容详细具体 请查收-This one of the few -- six players Responder Design Report details specific Check-This is one of four players to answer in a few electrical device designed to report detailed and specific please check-This is one of the
counter
- 计算频率程序 ，VHDL代码Quters软件编写，-VHDL Quters
Automachine_project
- verilog 语言写的自动售货机程序，系IC课程设计代码，QUARTUS -verilog language written in a vending machine program, the Department of IC curriculum design code, QUARTUS II
seven_lcd
- 七段数码管显示的时钟程序VHDL代码 ISE编译环境-SEVEN seg VHDL ISE CLOCK
verilog_code
- 《Verilog HDL程序设计教程》程序源码(王金明)-" Verilog HDL Programming Tutorial" program source code (Wang Jinming)
vhdltest
- 自己设计的几个VHDL程序，包括译码器电路，多路开关，比较器应用，和16乘8RAM电路，各模块及最终的顶层原理图和引脚我都已给好，希望对大家的学习有所帮助-A few of their own design VHDL procedures, including the decoder circuit, multiple switches, comparator applications, and 16 by 8RAM circuit, each module and final top-leve