资源列表
alu_wide2
- Generating a wider ALU from two small ones
counter_advanced
- A counter that starts from 0 and increments mod 16 on each rising edge of the clock
fsm_tb
- An odd parity checker as an FSM using VHDL
johnson_encoding_angle
- An FSM using VHDL and Johnson state encoding for states
FSKPSK
- 基于fpga的fskpsk信号产生器，可实现对1.2kHz和2.4kHz正弦波的采样-based on the fpga and fskpsk signal generator,can achieve sample to the 1.2kHz and 2.4kHz sin wave
ENT6
- 加法计数器的VHDL工程，程序，仿真图形-adder jishuqi de VHDL FANGZHEN ,CHENGXU
fdivide1
- 分频器的VHDL程序，完整的建立工程，编译，功能功能仿真，验证-fenpinqi de vhdlchengxu gongnengfnagzhen,yanzheng
moore
- mooor状态机的VHDL程序，代码，状态机，关键是分析各个状态之间的切换-mooor zhuangtaiji zhuagtaiji guanjianshi gege zhuangtai zhijian de qiehuan
CM12864
- cm12864液晶显示器的vhdl驱动代码，基于状态机的转换，实现显示功能。-descripe by the VHDL to drive the LCD cm12864,based on the FSM convertor,achieve the display function.
GPS
- 基于NIOS驱动ALTERA DE1开发板的GPS模块工程-based on the nios ii drive the gpa module of altera de1 develop board,it s only a reference project
LCDPS2
- 基于nios ii 驱动altera de1开发板上的lcd和ps2鼠标模块工程-based on the nios ii drive the lcd and ps2 module of altera de1 develop board
IICbus
- 基于nios ii 控制altera de1 开发板上iic总线实现与at24c02通信-Based on nios ii controlled altera de1 Development Board iic bus for communication with the at24c02