资源列表
afficheur
- Driver d afficheur de 4 chiffres de sept segments
read_solomon
- This project implements a parameterized Reed Solomon decoder for use in OFDM wireless systems.
cfft
- The FFT architecture is pipelined on a rank basis each rank has its own butterfly and ranks are isolated from each other using memory interleavers.-The FFT architecture is pipelined on a rank basis each rank has its own butterfly and ranks
BasicDES
- The BasicDES Cryptography Core is a small, fast implementation of the DES-56 encryption standard.
GUNMAOJI
- 全自动伺服驱动压销滚铆plc程序，日本进口的滚铆机原码-PLC
Twister_DDR_SDRAM_Board_Manual
- Twister DDR EP1C6Q240 FPGA 开发板 原理图，PCB,BOM-Twister Board Documentation Schematics, PCB and BOM Rev. B
t1
- tourbo encode pdf file we can study derive these folders
arm9_fpga2_verilog
- arm9 FPGA VERILOG 代码-arm9 FPGA VERILOG code
EnergyEfficientVLSIArchitectureforLinearTurboEqua
- Energy efficient for turbo encoder decoder
IterativeDecodingofBinary
- In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and deco
MapAlgorithm
- However, turbo equalizers can be computationally complex and hence require significant power consumption. In this paper, we present an energy-efficient VLSI architecture for such linear turbo equalizers. Key architectural techniques include elimi
RECURSIVEALGORITHMFOREFFICIENTMAPDECODING
- Early termination enables powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power.