资源列表
E1Tsi_TB
- TSI testbench for E1
FreqSynth
- Frequency synth example with primitives. Very simple.
AciAudioClks_TB
- Audio Codecs Clks synth for tlv
baudTest_TB
- baud testbenchfor sync and assync serial communication
E1SyncPkg
- The package constructor for E1sync example.
lcd
- FPGA控制lcd1602(verilog)-FPGA control lcd1602 (verilog)
seg
- 数码管显示（verilog） 自己写的 在数码管上显示01234567 动态显示-Digital LED display (verilog) himself wrote in the digital tube display 01234567 dynamic display
clock
- 这个程序是用verilog hdl语言编写，实现在数码管上显示时间，暂不支持调整-This program is written in verilog hdl to achieve in the digital tube display time, withhold support to the adjustment
clock
- verilog hdl代码 实现显示在数码管上显示时间，日期-verilog hdl code to achieve control in the digital display shows time, date. .
xilinxfpga
- Xilinx FPGA VerilogHDL 典型入门实例-Xilinx FPGA VerilogHDL
deinterleave
- CDMA.1X中，解交织的FPGA实现，程序基于VHDL编写，在XILINX开发板实现。-CDMA.1X, the solution of interwoven FPGA implementation, the program prepared based on VHDL, in the XILINX development board to achieve.
timer_set
- 这个是我自己编写的verilog代码，实现的功能是，在数码管上显示时间，按一个键，显示日期，长按一个键，显示秒表。。。时间日期可调-This is my own code written in verilog to realize the function of the digital tube display time, press a button, display the date, long press of a button, display Stopwatch. . . Time a