资源列表
qiangdaqi
- 六路数字式抢答器的主要仿真程序，容纳6组参赛的数字式抢答器，当第一个人按下抢答按钮时，其他组的按钮不起作用。当主持人按下“复位”按钮，所有组的按键才可用。-Six Road, a major digital answering device simulation program, up to 6 groups participating in the digital answering device, when the first one to answer in the button pres
FPGA
- FPGA入门系列实验教程 FPGA入门系列实验教程-Introduction to FPGA tutorial series of experiments
LEDsevensegmentdecode
- LED seven-segment decoding very good use of ~
CPU-to-VHDL
- CPU realization using VHDL CPU realization using VHDL-CPU realization using VHDLCPU realization using VHDLCPU realization using VHDL
counter
- 计数器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about counter for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example
Text-IO
- 基于VHDL的Testbench读取文件的编写，很有用的 基于VHDL的Testbench读取文件的编写，很有用的-VHDL Code text_io for the "Simple Test Bench" example VHDL Code about text_io for the "Simple Test Bench" example
inputoutput_textio
- 关于VHDL读取文件的testbench编写的ppt介绍，挺有用的-testbench for text_io,it is very useful,isn t it.testbench for text_io,it is very useful,isn t it.
OpticalFiber
- 利用VHDL语言编写的光纤通信，将上位机的命令通过主站处理后，用光纤发送到从站。-VHDL language using fiber-optic communication, the host computer commands through the main points are treated, the fiber is sent to from the station.
CLK_DIV_N
- 对输入的时钟进行分频输出:输出频率＝ 输入频率/(2*N+2-Of the input clock frequency output: Output frequency = Input frequency/(2* N+2
DECODE
- 利用状态机将并口发送的六组8位数据转换成串行正负脉冲数据发出。-Using the state machine will send the six groups of parallel data into serial 8-bit data to issue positive and negative pulses.
VHDL-for-FPGA
- 非常具体实用的VHDL程序，可以直接用。非常适合新手使用。-Very specific and practical VHDL program can be directly used. Very suitable for novices to use.
clock
- 用Verilog写的数字钟，用于单片机上实现-verilog