资源列表
pll
- 利用qaurtus的内的ip核定制锁相环实现对信号的倍频-The use of the ip qaurtus approved system PLL multiplier on signal
Digital_System_Design_with_SystemVerilog(draft).ra
- This book is intended as a student textbook for both undergraduate and postgraduate students.-This book is intended as a student textbook for both undergraduate and postgraduate students. The majority of Verilog and SystemVerilog books are aimed
DiskTest
- HDTUNE crack version
NIOS_LED_1
- FPGA开发 ATERA NIOS2处理器开发实例 控制LED灯-FRGA design
software
- ddr3 Test program for Altera FPGA Starter Kit
beep
- 通过用开发板上的蜂鸣器来实现发出警车鸣笛声-With the development board through the buzzer to send police car siren sound to achieve
DE1_D5M_LTM
- verilog new code for image sensor ov7660 version code
filtref
- fir vhdl programme altera
TMS470_P256_LCD
- TMS470 programme LCD
TMS470_P256_UART
- TMS470P256 programme C-TMS470P256 programme C
vhdl
- 用vhdl实现的抢答器程序。正弦波，锯齿波，三角波发生器程序。基于pwm技术的数码流水灯程序。计数器程序。-Responder with vhdl implementation process. Sine wave, sawtooth wave, triangle wave generator program. Pwm technology based on digital light process flow. Counter program.
8.27
- 四篇关于雷达杂波建模与仿真的论文 非常有用-4 Modeling and simulation of radar clutter is very useful paper