资源列表
jiaotongdeng
- 使用vhdl语言设计交通信号灯。由一条主干道和一条支干道汇合成十字路口，在每个入口处设置红、绿、黄三色信号灯，红灯亮禁止通行，绿灯亮允许通行，黄灯亮则给行驶中的车辆有时间停在禁行线外。主干道处于常允许通行的状态，支干道有车来时才允许通行，主、支干道均有车时，两者交替允许通行，主、支干道每次放行时间不得短于30S，在每次由绿灯亮到红灯亮的转换过程中，要亮4S黄灯作为过渡。 -Using vhdl language design traffic lights. By a main road a
watch
- 使用vhdl设计数码管显示的秒表； 能够准确的计时并显示； 开机显示00.00.00； 用户可以随时清零、暂停、计时；最大记时59分钟，最小精确到0.01秒。-Vhdl design digital display stopwatch accurate timing and display boot display 00.00.00 Users can be cleared at any time, suspend, timing 59 minutes maximum chronogra
lsd
- 用VHDL语言编写的流水灯，通过调试可用，希望可以给大家借鉴。-Light water using VHDL language, available through debugging, I hope you can learn from everyone.
saomiao
- 用VHDL语言编写的行列式键盘扫描程序，已经调试可用，希望对用到键盘的同学有所帮助。-Determinant keyboard scanning procedures, already using VHDL language debugging can be helpful to students to use the keyboard.
seg7_move
- 用VHDL语言编写的数码管动态显示程序，已经调试可用。-Digital dynamic display using VHDL language program debugging has been available.
ADV715
- it is a vhdl code it is a vhdl codei t is a vhdl codei t is a vhdl codei t is a vhdl codei t is a vhdl code-it is a vhdl code it is a vhdl codeit is a vhdl codeit is a vhdl codeit is a vhdl codeit is a vhdl codeit is a vhdl codeit is a vhdl codeit is
delay
- 一个基于FPGA的VHDL编写的延时程序。-A delay procedures based on FPGA VHDL written.
RS232
- RS232与FPGA的通信程序，经过QUARTUS II 7.1的测试，结果正确-RS232 communication program and FPGA, QUARTUS II 7.1 test results, correct
baseband-code-generator-program
- 基带码发生器程序设计与仿真.doc 源码程序并带有详细的注释，值得一看-The baseband code generator program design and simulation. Doc
RIPController
- 基于USB接口的发排卡设计,FPGA + Cy7c68013 + SDRAM-Based USB interface Fapai card design
fft8_3
- this code for fft program written in verilog-this is code for fft program written in verilog
fft16
- this 16 point written in verilog-this is 16 point written in verilog