资源列表
DDS
- 四通道DDS信号发生器,Four channel DDS signal generator-Four channel DDS signal generator
EDA
- 熟悉QuartusⅡ的Verilog HDL文本设计流程全过程，学习计数器的设计、仿真和硬件测试。-Familiar with Quartus II Verilog HDL text design process, learning counter design, simulation and hardware testing.
shift_reg_control
- vivado project for shift register in vhdl
interpolation
- vivado project file for down scaling of image by scale factor 2
dianti
- 实现电梯的相关控制系统，在开发板EGO1上实现，数码管显示相关的楼层和状态-dianti in verilog
ram
- 基于VHDL的教学实验机ram芯片连续读写-RAM chip based on VHDL continuous read and write
pcie_sg_dma_latest.tar
- 使用vhdl硬件描述语言实现的 PCIE DMA，资料详尽，与大家共享-vhdl for dma
C430
- 芯视清C4-30开发板的自检启动代码，里面有Audio_wm,DDR,LCD,PS2,VGA，等多个端口的自检程序-Core visual C4-30 development board self start code, which has Audio_wm, DDR, LCD, PS2, VGA, and many other self inspection procedures
Implement-a-CPU
- 在FPGA赛灵思基础3上使用Verilog HDL实现支持MIPS操作子集的CPU-Implement a CPU which supports a subset of MIPS operations using Verilog HDL on FPGA Xilinx Basys 3
OpenCores-Amber
- *硬件在OpenCore Amber ARM Core中实现-Trojan Hardware implemented in the OpenCores Amber ARM Core
OpenBTS-USRP1
- 用于OpenBTS USRP1 Cyclone FPGA比特流的Altera Quartus项目-Altera Quartus Project for OpenBTS USRP1 Cyclone FPGA bitstream
BASYS-3-Artix-7
- 使用BASYS 3 Artix-7 FPGA设计数字系统和数字逻辑的VHDL代码-VHDL code for designing digital systems and digital logic using the BASYS 3 Artix-7 FPGA