资源列表
verilog.tar
- please check the english descr iption.(an counter example written by verilog.)
ddr2_module
- 设计的DDR2的verilog代码.改代码实现读取DDR2的数据。(the code for DDR2.It is used for reading the data of DDR2)
asyn_fifo_204b_28
- 通用性异步fifo,性能非常好，推荐给大家(unverisal asyn fifo)
Vivado Reference Design R1
- vivado FPGA verilog VHDL
eiush
- Based on multi-document image obtained combining technique, Consider shadow rain attenuation and multipath effects Rapid expansion of random spanning tree algorithm.
OTU_SOHMUX
- cctv otu soh mux source
OTU_RXBLK
- cctv otu rx block source
kdw_tsohcnt
- cctv otu top source source block
isjtc
- Use serial programming examples matlab GUI implementation, Independent component analysis for image processing, Realize image watermarking, de-noising, plus noise and other functions.
ass
- FPGA sine wave, 让DE1学生版输出模拟信号。(analog ouput by DE1 developing board)
divide
- 使用Verilog硬件描述语言编写的分频功能，语言代码简短明了(Frequency division function)
uart
- FPGA的串口通信 v 文件，直接编译就可以串口通信了，波特率9600(FPGA serial communication, V file)