资源列表
pro001_buzzer
- 使用FPGA控制蜂鸣器的程序,用Verilog HDL设计,可以是蜂鸣器发出各种不同的声音-FPGA use buzzer control procedures, using Verilog HDL design, it is the buzzer sounded different voices
ASIC_TFT
- 彩色TFT液晶显示控制电路设计及其ASIC实现-color TFT LCD control circuit design and ASIC implementation
two_d_fir
- FIR FILTER verilog code-FIR FILTER Verilog code
fraq
- 基于VHDL语言的频率计具有高速计频，体积小的特点-based on VHDL or with the frequency or high frequency, small size characteristics
102416FFTVHDL
- 1024点，16位FFT VHDL 程序。1024点，16位FFT VHDL 程序-1024, 16 FFT VHDL procedures. 1024, 16 FFT VHDL procedures
dds_quicklogic
- 高手写的VHDL源码，实现DDS跳频器功能 请大家多提意见-experts write VHDL source code, the frequency-hopping DDS functionality Please speak up
szgysj
- 工业设计-industrial design
serial_VHDL
- FPGA进行串口通信的程序 VHDL编写的 -FPGA for serial communication procedure prepared by the VHDL
videodigitalsignalscontroller
- 用fpga技术实现基本的视频信号处理：主题程序；视频图象数据采集程序；sram的读写控制；测试程序-they simply use the basic technology of video signal processing : theme; Video data acquisition procedures; SRAM literacy control; test procedures
counter&adder
- counter and adder program by vhdl. Just enjoy it!-counter and adder program by VHDL. Just enj oy it!
vhdl_fifo
- 用vhdl编写的fifo队列.可以在maxplus2平台上使用.-using VHDL fifo prepared by the cohort. Maxplus2 platform can be used.
UP3_CLOCK
- 一个很小的时钟代码 一个很小的时钟代码-a small clock code, a small clock code, a small clock code a small clock code