资源列表
VHDL
- DEMO2 数码管扫描显示电路/DEMO4 计数时钟 DEMO5 键盘扫描设计/DEMO6 波形发生器/DEMO7 用DAC实现电压信号检测/DEMO8 ADC电压测量/DEMO9 液晶驱动电路设计-DEMO2 digital tube display circuit scan/DEMO4 count clock scan design DEMO5 keyboard/DEMO6 Waveform Generator/DEMO7 implementation by DAC voltage si
FinalFPMultiplier
- Simple 32 bit Floating point Multiplier
vga
- 硬件言语编写VGA时序控制，可用FPGA下载检测-vga
miffile
- 用matlab产生mif文件。(Altera的EDA软件，如maxplus，quartus等用到的初始化rom，ram等的文件格式)-Mif files generated by matlab. (Altera' s EDA software, such as maxplus, quartus used to initialize and so on rom, ram, such as the file format)
DDRSDRAMControllerverilogcode
- 这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。-This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Fron
led.control
- Control led with clock
all_bus_20050508.tar
- Vhdl cod for a bus.For sp2e
all_clock_20080928.tar
- Vhdl cod for a clock for sp3e
all_ram_20081116.tar
- vhdl cod for ram.For sp3e
mtd
- MTD定点浮点仿真，可直接用于fpga算法的仿真程序，产生了扫频信号，仿真直接输出系统频率响应函数，为系统测试带来好处-MTD fixed-point floating-point simulation, fpga algorithm can be used directly in the simulation program to produce a sweep signal, the direct simulation output system frequency response fun
modelsim7.2license
- 用于modelsim7.2的破解，里面有详细说明，很有用-For the crack modelsim7.2, which has detailed instructions, very useful
count_free
- 本程序是实现在用电话卡打电话时进行自动计费的功能，包括检测通话的种类，时间和余额检测等多项功能，此代码用veriloghdl编写已经调试通过编译。-Implementation of this procedure is used when the phone card to call the function of automatic billing, including the detection of the types of calls, time and number of functi