资源列表
Timer
- ep2c5 实现 定时器 verilog语言，quartus 2 仿真-verilog language to achieve ep2c5 timer, quartus 2 Simulation
VHDLclassicdesign
- VHDL经典设计，值得参考。压缩包里面文件直接用记事本打开即可。-VHDL design classic, it is also useful.
100vhdl-example
- VHDL的源码100例，包括加法、减法、存储、触发等，是初学者、开发人员的必备手册-VHDL source code of the 100 cases, including the addition, subtraction, storage, trigger and so on, is for beginners, developers must Manual
xunhuandeng
- 在spartan－3e上利用八个led实现流水灯效果-Spartan-3e in the use of eight led lights to achieve the effect of flowing water
FPGA
- FPGA 设计的四种常用思想与技巧-FPGA design ideas and techniques used in four
Verilog
- 硬件描述语言Verilog-Verilog hardware descr iption language
shuzi
- 一个用FPGA语言设计数字秒表的程序，有相关的源程序和说明-FPGA design using a digital stopwatch language of the procedures and instructions related to the source
FPGA-design
- FPGA设计全流程－软件综合使用、 -FPGA design of the whole process- the integrated use of software, FPGA design of the whole process- the integrated use of software,
OddFP
- verilog实现的奇数分频器 针对任何规模的奇数分频-verilog prescaler for the realization of the odd-numbered odd-numbered points of any size-frequency
CPI
- verilog实现的简易通用型CPI接口-verilog easy to achieve CPI general-purpose interface
InvMod_test
- verilog实现的1024位的大数模逆算法，引入RAM作为数据通道-verilog to achieve the 1024 Modular inverse algorithms, the introduction of RAM as a data channel
conv3
- Program to implement convolution through VHDL-Program to implement convolution through VHDL...