资源列表
SZZ
- 这是一个数字钟的VHDL语言，具有调时、调秒、调分功能，同时，还具有十二小时制向二十四小时制切换功能-This is a digital clock in VHDL language, with a tune, the tone seconds and sub-transfer function, while the system also has 12 hours to 24 hours the system switching function
renyimo
- 这是一个用VHDL编写的计数器，是一个任意模的计数器，不过是个异步的-This is a work written in VHDL counter, is an arbitrary module of the counter, but is an asynchronous
jtd
- 这是一个用VHDL编写的交通灯控制器，可以控制主干道和乡村公路的红绿灯-It is written in VHDL, a traffic light controller that can control the main roads and rural roads at the traffic lights
Principles_of_Verifiable_RTL_Design
- 本书详细讲解了可验证的RTL级代码的原理，为编写RTL仿真测试程序提供了理论基础-This book gave a detailed RTL-level code verifiable principles for the preparation of RTL simulation test program provides a theoretical basis for
Writing_Testbenches_Functional_Verification_Of_Hdl
- 本书作者为KLUWER，详细介绍了TESTBENCH程序的编写原理和技巧-The author of this book KLUWER, details the procedures for the preparation of TESTBENCH principles and techniques
risc8
- 简单的RSIC8，实现简单的CPU功能，可以提供大家学习-Simple RSIC8, to achieve a simple CPU features, can provide them to learn from
UART
- UART FOR VHDL hoping that it can give you a hand.
digitalpaobiao
- 用Verilog HDL语言编写的数字跑表源程序，已经通过综合编译及仿真。-With the Verilog HDL source code written in digital stopwatch has been through a comprehensive compilation and simulation.
yiweiDCTbianhuan
- 一维DCT变换的Verilog HDL源程序，在ISE中已经通过编译，可以参考里面的文档。-One-dimensional DCT transform Verilog HDL source code, in the ISE has been through the compilation, you can refer to inside the document.
RS232send
- 用Word文档描述了RS-232模块的发送。-With the Word document describes the RS-232 module to send.
DDS
- 分析了 中流水线结构及输入数据在其中移动的特点 提出了一种 流水线结构 给出了实现的方法并作了仿真 分析了对 电路性能的改进方案-DDS
AccelrateDesignPerformance
- FPGAs related material to accelerate design modules