资源列表
cores
- a core has been developed for your 32 bit fpu with a least 32x2 input 4 bit operator with round off and 32 bit output and 8 bit exeption data.
VHDL
- VHDL功能模块直接用。分有： 去抖，数码显示，任意分频。-VHDL modules directly. Points are: to shake, digital display, arbitrary frequency.
adder4
- 基于VHDL的4位加法器。 由4个一位全加器级联构成。-VHDL-based 4-bit adder. One consists of four full adder cascade.
Dlatch3
- 基于VHDL的触发器设计。 由一个电平触发的D触发器构成的上下边沿触发器。-Trigger-based VHDL design. Consists of a level-triggered D flip-flops up and down the edge of the trigger.
8051corelcd
- fpga上实现的51内核，带有LCD试验，顺利试验成功很好用。-on fpga implementation of 51 core with LCD test, successfully tested well with the smooth.
fulladder-using-half-adder
- half adder full adder using half adder in verilog
seven-segment-display
- seven segment diaplay
alarm_clock
- digital clock with alarm and control
cf_fft
- 用verilogHDL写的实现4096点FFT的算法，附带quartus ii工程.-VerilogHDL achieved with 4096-point FFT written algorithm works with quartus ii
UART
- URAT设计，系统包括五个模块，MCU模块，TX发送模块，RX接受模块，波特率产生模块，复位模块。-URAT design, the system consists of five modules, MCU module, TX transmit module, RX accept modules, baud rate generator module, reset module.
altera_cordic-Verilog
- altera_cordic sin cos altera_cordic sin cos-altera_cordic sin cos
frm_sync
- 此程序为帧同步程序，采用状态机的VHDL描述方式编写。-This procedure for frame synchronization procedures, using the state machine to prepare the way VHDL descr iption.