资源列表
uart_latest.tar
- 串口（UART）的verilog源代码，可以供设计参考-Serial port (UART) of the Verilog source code, can be used for reference in design
ledxy
- 通过VHDL实现跑马灯，以及仿真结果以及详细课程老师写的教程-Achieve marquees, as well as through VHDL simulation
01-vga_module
- verilog 实现vga显示这是第一个部分 共有五部分-verilog achieve vga display
03-vga_module_pic
- vga程序 verilog语言编写 共五个模块 这是第三部分-vga verilog language program of five modules This is the third part of the
04-vga_module_pic_color
- vga程序 verilog语言编写 共五个模块 这是第四部分-vga verilog language program which is part of the fourth of five modules
05-vga_module_ani
- vga程序 verilog语言编写 共五个模块 这是第五部分-vga verilog language program which is part of the fifth five modules
clock
- 针对开发板闹钟的设定，这仅是其中闹钟的一小块-Set the alarm for the development board, which is one of only a small alarm clock
EDAprogram
- 电子密码锁的设计，其中含程序图和流程各种东西-Design of electronic locks, which contains the program flow diagram and all sorts of things
kaoshi
- FPGA -计数器，29减法计数器。使用verilog hdl编写格式，cyclone I 系列EP1C3TC144芯片。-FPGA programming using 29 down counter, using verilog hdl written format, cyclone I series EP1C3TC144 chips.
ROM
- vhdl中的ROM程序，包括matlab表格程序，调用FPGA里的RAM实现ROM功能-The ROM vhdl procedures, including matlab spreadsheet program, call the FPGA to achieve ROM functions in the RAM
Vhdl1
- 简单的实用VHDL语言编写的LED跑马灯程序-Simple and practical LED Marquee VHDL language program
top
- 调用FPGA中的IP核的RAM的顶层文件-Call the FPGA IP core RAM top-level file