资源列表
eth
- 基于verilog语言的以太网接口的fpga实现，用在无线通信领域，供参考-The Ethernet interface based on verilog language fpga implementation, used in the field of wireless communications, for your reference
自定义PWM IP核，符合avalon总线
- 适合初学qsys、nios者，含tb文件，仿真通过，无bug
CCD_Sim
- 用verilog HDL语言编写的面阵CCD相机输出图像程序。-The CCD camera output image process using Verilog HDL language.
fir_lms
- 基于FIR滤波器的LMS自适应算法的FPGA实现-FIR filter based on LMS adaptive algorithm on FPGA
can
- CAN总线控制器的FPGA源代码，verilog语言编写，支持CAN2.0B协议。对CAN总线开发者非常有用。-FPGA CAN bus controller source code, verilog language, support CAN2.0 protocol B. Developers of CAN bus is very useful.
taxi
- 使用verilog语言编写的出租车计价器，适用于Quartus II软件，使用Cyclone IV系列开发板测试可用。-Use verilog language taximeter for Quartus II software, using Cyclone IV series development board test available.
PCIE_quartus13.1_tutorial2
- altera pcie avalon MM PCIE硬核仿真教程，器件Cyclone V，不同于教程1-avalon MM pcie sim tutorial，device Cyclone V，
3_Embedded_Systems_Lab
- altera max10 官网demo工程，嵌入式系统开发-max10 demo，Lab3 Embedded Systems Lab
4_Gesture_Sensor_Lab
- altera max10 手势传感器demo，2个传感器，nios2 实现-altera max10 Lab4 Gesture Sensor Lab，carry out with nios2
5_ADC_Lab
- altear max10 adc demo，实验使用了2个adc，最大支持18路adc-altear max 10 demo with 2 adc， max support 18 channel adc
6_USB_to_SDHC_Lab
- altera max10 USB demo，使用了phy，把开发板配置成U盘模式-altera max10 USB demo，using PHY device，design a U pan
7_BLE_WIFI_Lab
- altera max10 wifi demo， 非常有参考意义-altera max10 wifi demo，it is very usefull wo designers