资源列表
V-6-FPGA-Configure-Guide
- Xilinx公司的Virtex-6配置指南，是详细的官方指南-Virtex-6 configuration guide Xilinx company, is the official guide
zhongji
- 基于vhdl的dds信号发生器程序，具有一致十k调频功能，输出32k及64k正弦波-Based on the dds signal generator vhdl program has a consistent ten k FM function, 32k and 64k sine wave output
uart
- RS232串口的应用实例，其中用到了FIFO-RS232 serial port application, which uses a FIFO
juanji_3_3
- 自己写的3*3的高斯卷积模板，用Verilog在ISE上写的-Write your own 3x3 Gaussian convolution mask, using Verilog write on the ISE
sig_control
- 交通信号灯的verilog实现，里面包含有源程序和仿真图。-Verilog realize traffic lights, which contains the source code and simulation diagram.
wled
- verilog流水灯设计开发,已经经过验证的。-verilog water lamp design and development, has been proven.
mp3_player
- 用vhdl结合sopc编写的MP3的程序 可以在硬件上跑通 包含仿真程序-Written in conjunction with vhdl MP3 sopc program can run on the hardware via emulation program included
SPI
- verilog写的SPI总线程序，已经通过验证！-verilog write SPI bus program has been validated!
nand_model
- Nand Flash的Verilog代码，可以用于对nand flash操作的仿真-Verilog code of Nand Flash. It can be used for nand flash operate simulation.
PS2-verification
- It is made a verification of a FPGA board with a keyboard and a VGA
UART-finite-state-machine
- 基于Verilog语言的，用有限状态机实现Uart，很实用-UART design based on finite state machine
clock
- 设计一台能显示时、分、秒的数字电子钟，具体要求如下： （1）时计数器用24进制计时电路，分、秒计数器用60进制计分、计秒电路； （2）可手动校时，能分别进行时、分的校正； （3）能实现整点报时功能。 -Design a table can display hours, minutes and seconds of digital electronic clock, the specific requirements are as follows: (a) when the cou