资源列表
PL_2FSK
- 基于VHDl的2FSK调制！用的是altera的quartus11软件-Based on VHDl the 2FSK modulation
costasc_verilog
- 实现costas环，用verilog语言实现，缺少乘法器，可以自己添加-Realization of Costas ring, with the Verilog language implementation, the lack of multiplier, you can add their own.
CIS_drive
- 一个接触式图像传感器的驱动，Verilog语言，内含规格书-A contact image sensor driver, Verilog language, containing specifications
fir
- 用Verilog语言设计的一个数字FIR低通滤波器，很实用，通过modelsim仿真成功-Verilog language to design a digital FIR low-pass filter, very practical, through modelsim simulation success
LMS_filter
- 这是自适应滤波器，使用verilog代码来编写的，已通过了仿真，效果很好。希望能给大家好好分享！-This adaptive filter verilog code to write, through a simulation, with good results. I hope to give a good share!
FPGAPCI
- FPGA PCI板卡原理图 FPGA PCI板卡原理图
Google_Earth-Labview
- 可以实时显示经纬度坐标，高程及utc时间，并将地标在google-earth卫星图上显示-Latitude and longitude coordinates, elevation and utc time can be displayed in real time, and landmarks in the satellite images on google-earth
radar-controller-design-
- 某个雷达控制器的实现，当中的一些思想还是值得借鉴的，这是哈工大的硕士毕业论文，参考价值很大！-The realization of a radar controller, among some of the ideas or worth learning, This is HIT master' s thesis, a great reference value!
TEST
- Xilinx ///Microblaze中添加手动LCDIP的测试程序-Xilinx///Microblaze to add manually LCDIP test program
Ethernet-MAC-User-Guide
- 本文基于xilinx fpga ，v5,主要介绍如何用FPGA制作以太网-Based xilinx fpga, v5, describes how to use the FPGA making Ethernet
mux1_4
- 双4选1的数据选择器 输入信号：使用按键1、2、3、4 选择信号：使用按键7、8-Dual 4-to-1 data selector input signal: use keys 1,2,3,4 select signal: use keys 7-8
code
- 32位全加器 使用verilog写的硬件描述语言，xilinx芯片上运行过-32bits full adder