资源列表
SDI_PassThr_SZ
- Xilinx SDI参考设计，Verilog/VHDL源代码和相关文档等-Xilinx SDI pass through Verilog/VHDL source code
RD1054
- i2c接口的master ip 适用于lattice的器件-i2c master ip interface device for lattice
shuzipinluji
- 基于fpga的数字频率计的vhdl设计源码-Fpga-based digital frequency meter vhdl design source
multiplierunit
- VHDL/FPGA/Verilog 实现乘法器的功能-use VHDL/FPGA/Verilog multiplier unit
clock
- 基于VHDL硬件描述语言设计的多功能数字时钟的思路和技巧-VHDL hardware descr iption language based on multi-functional digital clock design ideas and techniques
422
- 422：实现232数据通过3160芯片转变为422数据,本程序通过编写422协议的VHDL程序达到转变的功能-422 ： 232 according to the realization by 3160 chips into 422, this program written agreement by 422 vhdl procedures to change function
RISC_cpu
- 基于RISC结构的8位微处理器的verilog源代码，很好的东西。-8-bit RISC-based microprocessor architecture verilog source code, a good thing.
fft_ug
- altera的FFT IP核的用户手册，介绍了如何使用ALTERA IP核生成FFT核，如何设置参数并讲述了如何仿真，适用于通信方面的FPGA设计工程师，学生。-altera' s FFT IP core user manual describes how to use the ALTERA IP core generated FFT core, how to set parameters and describes how to simulate, for communications, FP
CRC_Check
- crc校验的vhdl验证，模块分为编码组帧解帧解码模块-vhdl crc checksum verification, the module is divided into coding frame decoding module framing solution
EDA_dianzhen
- 使用verilog语言写的16*16的点阵，能够实现左移、右移、暂停、复位等功能，可以自己定制RAM，改变显示的内容。-Verilog language written using the 16* 16 dot matrix, to achieve left, right, pause, reset and other functions, you can customize RAM, change the display content.
fpgaPfirmwarePpc
- 用FPGA做USB2.0通信的实验，完成SLAVE FIFO模式下的数据传输，里面包括固件程序，还有上位机（Ｃ＋＋）程序。-USB2.0 communication with the FPGA to do the experiment, complete the SLAVE FIFO mode data transmission, which includes firmware, and PC (C++) program.
module
- 基于verilog的矩阵键盘和lcd1602显示-Verilog-based matrix keyboard and display lcd1602