资源列表
paobiao
- 一个基于FPGA的数字跑表系统的设计，最小单位是百分表位。采用十进制进位。-FPGA-based digital stopwatch system design, the smallest unit is a digital dial indicator. Binary using the metric system.
SDRAM
- 这个是一个基于FPGA的SDRAM控制器系统，实现对SDRAM的读写操作，用来实现时序的控制-This is an FPGA-based SDRAM controller system, the read and write operations to SDRAM to achieve the control of timing
stopwatch
- VHDL语言设计的秒表，实现计时功能，实现报时功能，并且通过硬件实验。-VHDL language design stopwatch, timer function of the realization, the realization of time functions, and through hardware experiments.
taxi
- VHDL开发环境，出租车计费系统，实现起步10元，每增加一公里，自动上涨2元。-VHDL development environment, taxi billing system to achieve the initial 10 yuan for each additional mile, automatic up 2.
elevator
- VHDL开发环境，电梯控制系统，实现电梯的上下传送控制。-VHDL development environment, elevator control system, transmission control up and down elevators.
Verilog
- code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx-code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx
CardBusIP_v1.0
- VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用-CARDBUS IP CORE
single_clock_divider.tar
- 关于基数分频技巧设计,基于VHDL语言,对实际设计有帮助-DIVIDE
LCD
- TS1602 LCD 显示的例子,包括,LCD的初始化,显示一行文字,清屏-TS1602 LCD display examples, including, LCD initialization, showing a line of text, the Qing Ping
shukongfenpin
- 数控分频器的输出信号频率为输入数据的函数。用传统的方法设计,其设计过程和电路都比较复杂,且设计成 果的可修改性和可移植性都较差。基于VHDL 的数控分频器设计,整个过程简单、快捷,极易修改,可移植性强。他可利用 并行预置数的加法计数器和减法计数器实现。广泛应用于电子仪器、乐器等数字电子系统中。-NC divider output signal frequency is a function of input data. Using traditional methods of desig
zhushaoyong
- 设计并制作一个14键单音电子琴预先存入一些曲谱电路在4Hz的时钟控制下自动播放 通过220V电源适配器给电路提供工作电源-Design and production of a 14-key electric piano tone into a number of music scores advance in 4Hz clock circuit under the control of automatic play through 220V power adapter to provide
B(f)
- 自己编的VHDL的波形发生器 做信号的可以-BOXING