资源列表
BJDJ
- 实现步进电机的驱动控制，可以实现精准步距角控制(Stepper motor driver control)
FPGA分频
- xilinx spant6 PLL分频，生成4个不同频率的时钟，实现LED闪烁。(xilinx spant6 PLL frequency division)
DS_FH
- fpga与通信系统的结合设计，对初学者会有一定的启发，扩频通信系统(to strengthen your ability and combine the programmer with the technology of spectrum system)
SD_audio
- 编写verilog 程序 利用fpga 读取sd卡音频播放(Use FPGA to read SD card audio playback)
can_loopback_test
- 实现了can控制器Verilog编程使用niosII 开发平台(Can controller Verilog programming, the use of niosII development platform)
60jishuqi (2)
- 这是一个可以记到60的计数器，可用于数字钟层次化设计。(This is a counter that can be recorded to 60, and can be used for the hierarchical design of digital clock.)
DE2_CAMERA
- DE2 camera interface code
第2章_Quartus_II_使用方法
- I hope the PDF file I shared is very useful for your work. Thanks
第2章_Quartus_II原理图输入
- I hope the PDF file I shared is very useful for your job. Thanks
第3章__Quartus_II原理图输入法深入
- I hope the PDF file I shared is very useful for you. And I also wish I can learn some useful knowledge from this web.
第5章_QuartusII应用向导(原理图输入方法)1
- I hope the PDF file I shared is very useful for you.
full_adder
- 全加器，可以实现数据的加法运算，有来自低位的进位和向高位的进位。(Full adder, data can be added to the operation, there are low from the carry and to the high carry.)