资源列表
usb_ctrl
- USB2.0 控制接口代码，可用于与上位机进行通信传输。-USB2.0 interface controller，can be used for communication between host(computer) and FPGA board.
iic_ctrl
- 基于Verilog的IIC接口，使用状态机实现，可以支持速率参数化。-implement IIC master controller by using Verilog language.
spi_master
- SPI 控制接口，可支持传输位数的动态配置。-SPI standard controller interface，can support configure dynamically.
DDS
- dds采用查表法的方式实现，有MATLAB取样。基本的方法-DDS is implemented by look-up table, with MATLAB sampling
IRcoder
- 利用Verilog HDL程序实现红外线解码数码管显示,遥控器按下数字显示在FPGA开发板的数码管上.-Using Verilog HDL program to achieve infrared decoding digital display,the remote control presses the digital display on the digital board of the FPGA development board.
SRAM
- 静态随机存储器,它是一种具有静止存取功能的内存，不需要刷新电路即能保存它内部存储的数据。-Static random access memory, which is a memory with a static access function, do not need to refresh the circuit that can save its internal storage of data.
mux8
- 利用拨码开关，实现四位二进制与四位二进制的乘法器，结果转换为十进制，并通过数码管显示。-Using the DIP switch to achieve four binary and four binary multiplier, the results are converted to decimal, and through the digital display.
uart
- （1）利用串口实现发送功能，即利用计算机上的串口调试小助手定时显示“HELLO WORLD”字样；（2）利用串口实现接收功能，并将接收到的字符再通过串口发送到计算机上的串口调试小助手上显示，例如：利用串口小助手的手动发送功能向串口发送“Good Good Study，day day up”，然后利用FPGA实现转发，将字符从串口发送回串口调试小助手显示。-(2) the use of serial port to achieve the receiving function, and the r
tiaozhi
- 基于verilog HDL的数字正交解调FPGA实现，仿真结果验证正确，IDE为vivado 2014- U57FA u4E8Everilog HDL u7684 u6570 u5B57 u6B63 u4EA4 u89E3 u8C03 u5B9E u73B0 uFF0C u4EFF u771F u7ED3 u679C u9A8C u8BC1 u6B3 u786E uFF0CIDE u4E3Avivado 2014
jietiao
- 基于verilog HDL的数字正交（调制）FPGA实现，仿真结果验证正确。vivado 2014- U57FA u4E8Everilog HDL u7684 u6570 u5B57 u6B63 u4EA4 uFF08 u8C03 u5236 uFF09FPGA u5B9E u73B0 uFF0C u4EFF u771F u7ED3 u679C u9A8C u8BC1 u6B63 u786E u3002vivado 2014
spi_flash_controler
- w25q64 spi flash verilog code .use xilinx ise .
uart_tx
- 基于FPGA的串口发送模块设计及仿真,可移植代码-Design and Simulation of serial port sending module based on FPGA，portable code