资源列表
FSM
- 这是一个有限状态机的设计，并且用来测试一个学列，七段数码管输出检测序列的值，有限状态机用三段式编写。- This is a finite state machine design, and used to test a school, seven-segment digital output detection sequence value, the finite state machine with three-stage preparation.
register
- 用Verilog实现了一个基本寄存器，并且用仿真和led灯来显示了读写数据。-Using Verilog to achieve a basic register, and led lights and simulation to show the read and write data.
FPGA_拉格朗日插值_IP
- fpga实现拉格朗日插值，本工程采用verilog语言实现，可直接使用
code_lagrange_interpolation
- 使用verilog实现拉格朗日插值，很有使用价值，有需要的可以参考一下-Use verilog to achieve Lagrange interpolation, very useful value, there is a need to refer to
1602verilog
- 采用Verilog语言完成了1602液晶屏的驱动显示-Using Verilog language to complete the 1602 LCD screen driver display
Frequce
- 能测量频率，并且能测占空比10 90 ，还能产生1M 占空比10 的脉冲波- 能测量频率，并且能测占空比10 90 ，还能产生1M 占空比10 的脉冲波 Can measure the frequency, and can measure the duty cycle 10 90 , but also can produce the 1M duty cycle 10 of the pulse wave
ExperimentoCap9
- Question cpa 9 of the an book in portuguese
VGAController
- Easy VGAController in vhdl
8a
- 2 Flip Flops in VHDL
soma_loka
- Sum make in vhdl code
rs_232
- Comunication rs232 in vhdl
equalizer
- This the code for the channel equalizer and the test bench for this in the verilog code.-This is the code for the channel equalizer and the test bench for this in the verilog code.