资源列表
cgra-full
- verilog code for cgra architecture
bus-invertcoding
- verilog code for bus invert coding
fibonaccicode
- verilog code for fibonacci codes
random_num
- Random number generation
Array_slice_1Dx1D_of-bit-vector
- Array slice 1dx1D for individual access of element
RAM1
- Ram source code 32-bit.
MatrixAdd
- Matrix addition for matrix operation
DCT8_slow
- 8x8 DCT architecture for image compression
ADDA
- AD9708适合FPGA黑金开发板，能够高效的学习黑金开发板-AD9708 suitable FPGA development board black gold, black gold can be an effective learning development board
com5005_003
- VHDL source code for 5505
com1600template_002f
- VHDL source code of 1600 M-VHDL source code of 1600 MII
converter
- 多位2-10进制转换与10-2进制转换，用十进制加法器实现-2-10 and 10-2 convert binary number base conversion, decimal adder realization