资源列表
fft_core_test
- 基于FPGA的FFT的IP核实现，有其详细源码，采用verilog语言编写，内容详细-The FFT based on FPGA IP core implementation, has its source in detail, using verilog language writing, detailed content
24T
- 24小时周期时钟设计，通过quartus模块实现24小时周期时钟，包含模拟的时钟脉冲。-24 hour cycle clock design, through the quartus module to achieve a 24 hour cycle of the clock, including analog clock pulse.
Ripple-carry-adder
- Ripple carry adder using system verilog
Sequential-Multiplier
- sequential multiplier using system verilog
state_led_one
- 基于verilog HDL的状态机8位流水灯（一个按键控制左转和右转），开发环境Diamond 3.7(64-bit)；FPGA采用LCMXO2-1200HC-4MG132C；时钟25M；开发板：与非网小脚丫-Based verilog HDL state machine eight light water (a key control buttons turn left and turn right), the development environment Diamond 3.7 (64-b
write
- 使用golang生成一个coe文件，初始化rom。其中随机产生10000个数值作为初始化值-Use golang generate a coe file to initialize rom. Wherein the randomly generated value as the initial value 10000
source
- FPGA串口，verilog HDL串口收发程序-FPGA serial, verilog HDL serial transceiver procedures
shuzipaobiao_all
- VErilog源码，数字跑表数码管显示，按键控制-VErilog source, digital stopwatch digital display, control buttons
yiweijicunqi
- 移位寄存器的原理图设计，基于quartusII软件。-Shift register schematic design, based quartusII software.
DE2-115_labs_vhdl
- DE2-115板上的，lab-exercise的PDF历程-, Lab-exercise of PDF course DE2-115 board
DE2_115_pin_assignments
- de2-115引脚的配置，quartusII的设置-de2-115 configuration pins, quartusII settings
liushuideng
- 流水灯，控制方向，对系统时钟进行分频，奇偶数闪亮-Water lights, control direction, the system clock frequency, odd even flashing