资源列表
VGA
- 时序逻辑 VHDL 实现VGA显示接口 串口连接-vhdl vga
dds
- 在quartus软件上，采用verilog实现DDS功能。- using verilog realize DDS function On quartus software.
HDL_Syn_V3.1
- 哈夫曼编码 包括synthesis优化。 Huffman encoding verilog code including synthesis optimization.-Huffman coding involves synthesis optimization. Huffman encoding verilog code including synthesis optimization.
combine
- 代码主要实现小车的红外避障以及超声波测距，进而控制点小车跟随人行走。-The main code of the car infrared obstacle avoidance and ultrasonic ranging, and then control point car to follow people walking.
test1
- 并编写机器码程序求1至100内能被4整除的全部自然数的和，验证该CPU核心的正确性。- write machine code program for 1 to 100 of all natural number can be divisible by 4 and, verify the correctness of the CPU core.
digi_clk
- Digital watch in VHDL.
clk_div
- Clock divider in VHDL.
buffer_tri_state
- Buffer tristate in vhdl
BCD_to_7_seg_decoder
- BCD to 7 segments display decoder
Verilog
- FPGA开发板资料Verilog，53个例程-fpga Development board materia
FFT_n4
- FFT n point 4096 1024 -FFT n point 4096 1024 ...
uart_server
- 24路串口转1路串口服务程序, 包括FIFO模块，串口接收，发送模块，定时器模块，检测控制模块等。采用Verilog编写-24 way serial ports to 1 serial port, including FIFO module,RX module,TX module, timer module, detection and control module, etc.. Verilog preparation