资源列表
bfm
- Bus Functional Model Design
bzfad
- BZFAD Code in Verilog Possible Bugs
bzfadmultiplier
- BZFAD MUltiplier Code In Verilog Possible Bugs
Preemptive_answer
- 代码是多路抢答器,抢答精度极高，程序简单-primitive_answer
Viterbi_Decoder
- viterbi decoder for convolution encoder
bishe3
- 以复杂可编程逻辑器件(CPLD)为核心的新型通用数字触发器-Based on complex programmable logic device (CPLD) as the core of the new universal digital trigger
verilog-led
- 此程序是Verilog语言编写的一个流水灯程序，简单易行-This program is written in Verilog language a light water program, simple and feasible
PIPELINE
- （包含详细说明文档和简单汇编转机器码翻译器）五级流水线实现MIPS指令集（30条）含异常处理。结构采用多分支预测结构（基于历史的动态分支预测）-(Contains detailed documentation and compilation turn simple machine code translator) five pipelined MIPS instruction set (30) with exception handling. Structure using multi-bran
uart_top
- FPGA verilog hdl UART232 工程及相关源程序，可直接使用-FPGA verilog hdl UART232 project and source code use it directly
top_hwx
- quartus 红外遥控接收解码工程以及相关代码。可直接使用-quartus ii hwx project and source code 毛can be directly used
CacheFromScratchFinalWeek_ise12migration
- VHDL implementation of an 8-bit multilevel cache. Produces timing diagrams when run on a suitable IDE such as Xilinx.
VGA
- quartus ii verilog hdl 实现VGA时序及显示的工程和源程序 -quartus ii verilog hdl vga timing project and source code