资源列表
chap7
- 本程序是关于学习VERILOG语言的案例，方便读者快速掌握VERILOG语言的基本语法，操作等-This program is about learning the language of the case VERILOG to allow readers to quickly master the basic syntax of the language VERILOG, operation, etc.
Archive
- i enclosed the win socket
pingp16
- 改进后的pingpong实例，增加球数至16个，用于检测vga输出,并由相应ucf文件-Improved pingpong example, to increase the number of balls 16, for detecting vga output
generic_avalon_sram
- 一个比较有参考价值的sram IP核，对SOPC感兴趣的人士有一定的指导意义！该程序是采用avalon总线，可以直接内嵌进SOPC Builder。
vhdl-implementation-of-huffman-algorithm
- VHDL implementation of HUFFMAN algorithm
ddr_ram
- ddr_ram, ddr 工程调试文件，和测试向量激励-ddr_ram, ddr engineering code and test incentives document
CPSK
- CPSK调治程序 -CPSK modulating procedures CPSK modulating procedures CPSK modulating procedures
DM9000_net
- fpga操作dm9000的代码例程 fpga操作dm9000的代码例程-FPGA operation dm9000 code routines FPGA operation dm9000 code routines
time_check
- 通信主从机双向系统时钟同步，用于扩频、跳频等。由从机发起时间校准请求，主机回复时间信息，达到主从机的时钟同步。-Slave two-way communication between the host system clock synchronization for spread spectrum, frequency hopping and so on. Initiated by the slave time alignment request, the host response time
FIFO.tar
- FIFO design VHDL/Verilog design
zhuangtaiji
- 十种状态机例子（VHDL）包括米勒型和莫尔型的状态机。-Dozens of examples of state machine (VHDL), including Miller and Moore type state machine.
1602
- 基于Verilog的液晶初始化程序。本程序可初始化基于ＦＰＧＡ的１６０２模块。-Verilog-based LCD initialization procedure. This procedure can initialize the based FPGA module 1602.