资源列表
Verilog
- 七段数码管译码器.(Verilog)[FPGA]第一个Verilog程序,七段共阴数码管摸索了好几天,终于能完成敲入代码、综合、仿真、绑定引脚至下载的全套工作了 -. 七段数码管的lookup table module SEG7_LUT ( input [3:0] iDIG, output reg [6:0] oSEG ) always@(iDIG) begin case(iDIG) 4 h1: oSEG = 7 b1111
counter.tar
- 基於verilog 所製成的counter程序，可以向上計數-Verilog made based on the procedures of the counter can count up
HCRB
- 设计要求：设计一个自动售货机控制系统。该系统能完成对货物信息的存储、进程控制、硬币处理、余额计算、显示灯功能。可以管理4种货物，每种货物的数量和单价在初始化时输入，在存储器中存储。用户可以用硬币进行购物，按键进行货物选择；售货时能根据用户输入的货币，判断钱币是否足够，钱币足够则根据顾客要求自动售货，钱币不足则给出提示并推出；能够自动计算出应找钱币余额、库存数量并显示。-Design requirements: design of a vending machine. The system can
QPSKmapping
- CODE OF QPSK:The mapping module used is QPSK type of modulation
counter
- counter that counts by generating clock.
task
- task verilog code basic example-task verilog code basic example
traffic
- 用vhdl语言设计的十字路*通信号灯控制：共有四种状态。-Language design using vhdl traffic light controlled crossroads: A total of four states.
FPGA_key
- 本程序是在VERILOG语言的基础上编写键盘程序，理论上键盘是很容易实现的，但因为要考虑消抖的因素，所以，会复杂一些。-This program is prepared based on the VERILOG language keyboard program, in theory, the keyboard is very easy to implement, but because the factors to consider debounce, therefore, be more
HDB3
- 基于FPGA的HDB3码的译码器代码，主要用于译码器-HDB3 yards on FPGA decoder code, mainly for the decoder
freq_div2
- 采用VHDL语言设计的分频器，仿真和实际电路板都测试过，没问题。-Divider using VHDL design, simulation and actual circuit boards are tested, no problem.
counter_vhd
- Counter is used to count the value of the memory register in the digital circuits-Counter is used to count the value of the memory register in the digital circuits....
pulse
- 一个产生可调频率和可调占空比Verilog源代码，希望对你起到作用-A variable frequency and variable duty cycle generates Verilog source code, you want to play a role