资源列表
code_VHDL
- 无流水无cache的cpu代码，基于verilog，CPU 芯片的主频是 15.3MHz,FPGA 器件的资源占用率为 28 -cpu code with no water nor cache
manche_code_Verilog
- mancher_code Verilog example
34343535535
- 基于FPGA的数字电压计的实现源代码和详细说明-the digital voltage based on FPGA
digitalvoltemterdesign
- FPGA的关于数字电压计的设计源代码，已验证可行-FPGA on the digital voltmeter design source code, has been proven feasible
21
- 是FPGA程序。题目是USB接口应用系统设计实例
ads8132_verilog
- 关于ADS8132的硬件语言verilog HDL描述，精简实用，而且准确，已通过工程验证-About ADS8132 verilog HDL hardware descr iption language, streamlined and practical, and accurate, has been verified by the project
TLC1556
- 使用10位串行DA芯片TLC5615将数字信号转换为模拟信号，开发板DA芯片VDD=5V,VREF=3.3V 计算公式：Vout=VREF*(N/1024) N为10位二进制码-Use DA chip TLC5615 10 serial digital signal into an analog signal, the board DA chip VDD = 5V, VREF = 3.3V formula: Vout = VREF* (N/1024) N is 10-bit binary
verilog
- 曼彻斯特编码的verilog实现,复制到quartus II可用-Manchester verilog realize the code,Copy to quartus II available
AEScoremodules
- AES decoder aes_dec.vhdl AES encoder aes_enc.vhdl Package used by rest of design aes_pkg.vhdl Key Expansion component for AES encoder and decoder key_expansion.vhdl -AES AES encoder decoder aes_dec.vhdl aes_ enc.vhdl Package used by rest
SRAM
- 通过对一个数据写进sram与从里面把这个数据读出。来理解sram的基本操作方法-Through a data written into the SRAM, and this data is read out from the inside. To understand the sram basic operation method
2
- 熟悉和了解SOPC系统的构建； 了解NiosiiIDE的使用和调试。 -Knowledge and understanding of SOPC system construction understand NiosiiIDE use and debugging.