资源列表
async_fifo-and-verilog
- 异步fifo的详细原理分析说明及verilog源代码，经典推荐！-Detailed descr iption of the principles and analysis of asynchronous fifo verilog source code, the classic recommendation!
altera_avalon_checksum
- altera的avalon总线校验代码,是进行sopc开发的参考
xors_1
- this xor gate in vhdl run under active hdl-this is xor gate in vhdl run under active hdl
rtl
- 基于VERILOG的SDRAM控制程序，是目前主流设计方法-Control procedures based on VERILOG of SDRAM, is the main design
PIC_EEPROM
- 改程序实现了PIC单片机读取外部EEPROM主要是通过串行SCI方式进行读取。-Program for the PIC microcontroller to change the external EEPROM read mainly by way of reading the serial SCI.
VMM_example
- This is a VMM example System Verilog written for a router DUT-This is a VMM example System Verilog written for a router DUT
picoblaze_interrupt_controller_latest.tar
- picoblaze microcontroller
altlvds_DesignExample_ex5
- 在FPGA中调用LVDS，其中包括仿真和源代码。-using fpga lvds
quartus-ii-automatically-assign-pins
- quartus ii 中自动分配管脚的三种方法-quartus ii automatically assign pins are three ways
DiceFinal
- vhdl source code for dice game
ddsProm
- dds 频率可控，32位 输出为12位 已含有.hex文件，直接装载致ROM即可~-dds frequency-controlled, 32-bit output is 12 already contains. hex file can be loaded directly caused ROM ~
lcd_controller
- verilog写的LCD的ip，avalonMM总线操作-verilog LCD ip, avalonMM bus operation